The present invention relates to calculating critical paths in signal propagation within an integrated circuit (IC). When analyzing a particular IC design, computer tools estimate signal propagation delays throughout the IC in order to determine the maximum operating frequency of the IC. Electric signals reach destination registers through intermediate registers, gates, buffers, etc. Signals may propagate to destination registers through different paths, thus causing the different signals to reach a destination register at different times depending on the signal delay thorough each of the paths.
Timing analysis tools often use timing graphs to analyze signal propagation, such as the propagation delays from source registers to destination registers. A source register is a register that has at least one timing path from itself to another register. A destination register is a register that has at least one timing path arriving from another register. A register can be both a source register and a destination register.
The design engineer is interested in finding out what are the most critical paths in the IC to determine if the application and operating frequency are appropriate for the design. Given the large amounts of registers, gates, buffers, wires, etc., in today's ICs, the calculation of all possible paths requires vast amounts of time and computer resources. It is in this context that embodiments of the invention arise.